1. Field of the Invention
This invention relates to an FM(frequency modulation) demodulation circuit which demodulates a frequency modulated signal, and more particularly to an FM demodulation circuit formed from a quadrature detection circuit.
2. Description of the Related Art
FM demodulation circuits for demodulating a frequency modulated signal include a delay detection circuit, a pulse counting detection circuit, a quadrature detection circuit and so forth. In recent years, a quadrature detection circuit which makes use of a resonance circuit is used principally.
For a quadrature detection circuit, two circuit constructions are-available including a circuit which makes use of a frequency to phase characteristic of a resonance circuit and another circuit which makes use of a frequency to impedance characteristic of a resonance circuit. The former quadrature detection circuit which makes use of a frequency to phase characteristic of a resonance circuit is used popularly.
Of the FM demodulation circuits which include a quadrature detection circuit, a conventional quadrature detection circuit which makes use of a frequency to phase characteristic of a resonance circuit is described with reference to FIGS. 1 to 5.
Referring to FIG. 1, the conventional quadrature detection circuit which makes use of a frequency to phase characteristic of a resonance circuit includes amplitude limiting circuit 101 for limiting the level of frequency modulated input signal f.sub.in to a predetermined level, phase conversion circuit 102 for outputting signal f.sub.A having the same phase as that of an output signal of amplitude limiting circuit 101 and signal f.sub.B obtained by converting a frequency variation of the output signal of amplitude limiting circuit 101 into a phase variation, multiplier 103 for outputting a signal of a phase difference between two signals f.sub.A and f.sub.B outputted from phase conversion circuit 102, and low-pass filter (hereinafter referred to as LPF) 104 for integrating the output signal of multiplier 103.
Phase conversion circuit 102 includes resonance circuit 105 having series resonance frequency f.sub.s and parallel resonance frequency f.sub.p in a frequency characteristic thereof, resistor R101 connected in parallel to resonance circuit 105, and capacitance C101 connected in series to resonance circuit 105 and resistor R101 and inserted in a line along which signal f.sub.B is transmitted.
Resonance circuit 105 is formed from a well-known LC resonance circuit, ceramic discriminator or like circuit.
As shown in FIG. 2A, since resonance circuit 105 exhibits an inductance characteristic in frequency region f.sub.w1 which satisfies series resonance frequency f.sub.s .ltoreq.f.sub.w1 .ltoreq.parallel resonance frequency f.sub.p, the phase of the output voltage leads by 90 degrees with respect to the phase of the input voltage. On the other hand, since resonance circuit 105 exhibits a capacitance characteristic in frequency regions f.sub.w2 and f.sub.w3 which satisfy f.sub.w2 .ltoreq.f.sub.s and f.sub.p .ltoreq.f.sub.w3, respectively, the phase of the output voltage lags by 90 degrees with respect to the phase of the input voltage.
Here, if amplitude limiting circuit 101 is connected in parallel to resonance circuit 105 as shown in FIG. 1, then such a frequency to phase characteristic as illustrated in FIG. 2B can be obtained. Where such a frequency to phase characteristic as illustrated in FIG. 2B is utilized, if the frequency of input signal f.sub.in changes to f.sub.1, f.sub.2 and f.sub.3, then the phase of the output voltage of resonance circuit 105 changes to .theta..sub.1, .theta..sub.2 and .theta..sub.3, respectively. The inclination of the frequency to phase characteristic is determined by the resistance value of resistor R101 connected in parallel to resonance circuit 105. It is to be noted that, for resistor R101, a fixed resistor is used normally.
Multiplier 103 is usually formed from such an EX-NOR (exclusive OR inverting outputting) circuit as shown in FIG. 3. The relationship of output Y to inputs A and B of the EX-NOR circuit is indicated by the following table.
______________________________________ A B Y ______________________________________ 0 0 1 1 0 0 0 1 0 1 1 1 ______________________________________
In the construction described above, an output signal of amplitude limiting circuit 101 is inputted to phase conversion circuit 102. Phase conversion circuit 102 outputs signal f.sub.A of the same phase as that of the output signal of amplitude limiting circuit 101 and signal f.sub.B obtained by converting the frequency variation of the output signal into a phase variation.
Here, when the frequency of input signal f.sub.in is f.sub.1, f.sub.2 and f.sub.3, the phase of signal f.sub.B exhibits such relationships to the phase of signal f.sub.A as illustrated in FIG. 4 due to the delay (-90 degrees) of the phase by capacitance C101 and the displacement in phase by resonance circuit 105. In this instance, signal f.sub.Y of the phase difference between two signals f.sub.A and f.sub.B is outputted from multiplier 103. This output signal f.sub.Y of multiplier 103 is integrated by LPF 104. Consequently, such a demodulation output characteristic as illustrated in FIG. 5 can be obtained from the FM demodulation circuit.
The inclination of the demodulation output characteristic of the FM demodulation circuit is usually called demodulation sensitivity. The demodulation sensitivity is indicated by the inclination of the frequency to phase characteristic of the phase conversion circuit 102, and the inclination is determined by the value of resistor R101 connected in parallel to resonance circuit 105.
Next, a quadrature detection circuit of the bridge type which makes use of a frequency to impedance characteristic of a resonance circuit is described with reference to FIGS. 6 to 9.
Referring to FIG. 6, the conventional quadrature detection circuit which makes use of a frequency to impedance characteristic of a resonance circuit includes amplitude limiting circuit 111 for limiting the level of frequency modulated input signal f.sub.in to a predetermined level, phase conversion circuit 112 for outputting signal f.sub.A of the same phase as that of an output signal of amplitude limiting circuit 111 and signal f.sub.B obtained by converting the frequency variation of the output signal of amplitude limiting circuit 111 into a phase variation, multiplier 113 for outputting a signal of a phase difference between two signals f.sub.A and f.sub.B outputted from phase conversion circuit 112, and LPF 114 for integrating an output signal of multiplier 113.
Phase conversion circuit 112 includes resistors R111, R112 and R113, and resonance circuit 115 having series resonance frequency f.sub.s and parallel resonance frequency f.sub.p in a frequency characteristic thereof. A bridge circuit is formed from resistors R111 to R113 and resonance circuit 115.
Resonance circuit 115 is formed, similarly to a quadrature detection circuit which makes use of a frequency to phase characteristic of a resonance circuit, from an LC resonance circuit having series resonance frequency f.sub.s and parallel resonance frequency f.sub.p in a frequency characteristic thereof, a ceramic discriminator or some other suitable device.
In the construction described above, resonance circuit 115 exhibits an inductance characteristic in a frequency region between series resonance frequency f.sub.s and parallel resonance frequency f.sub.p. Where the impedance of resonance circuit 115 in this frequency region is represented by j.omega.L, phase conversion circuit 112 is equivalent to such a bridge circuit as shown in FIG. 7.
Here, by setting R111=R112=R113=R with frequency f at which (f.sub.s +f.sub.p)/2 is satisfied and placing j.omega.L=R, current I.sub.1 flowing through terminals a, b and c and current I.sub.2 flowing through terminals a, d and b are given by the following expressions: EQU I.sub.1 =V.sub.in /(R111+R112)=V.sub.in /2R EQU I.sub.2 =V.sub.in /(R113+j.omega.L)=V.sub.in /2R
As seen in FIG. 8, current I.sub.2 is delayed in phase by .psi..sub.d =tan.sup.-1 (.omega.L/R) from V.sub.in.
Accordingly, as seen in FIG. 9, as the frequency (.omega.=2.pi.f) of input signal f.sub.in varies, then the value of the impedance (j.omega.L) of resonance circuit 115 varies and the phase difference between V.sub.in and current I.sub.2, also the phase difference between V.sub.in and V.sub.out of the bridge circuit shown in FIG. 7 varies.
Consequently, similarly to a quadrature detection circuit which makes use of a frequency to phase characteristic of a resonance circuit, signal f.sub.B whose phase varies in response to a frequency variation of input signal f.sub.in can be obtained.
Multiplier 113 is formed from an EX-NOR circuit and outputs a signal of a phase difference between two signals f.sub.A and f.sub.B. By integrating this output signal f.sub.Y of multiplier 113 by LPF 114, such a demodulation output signal as illustrated in FIG. 5 can be obtained similarly to a quadrature detection circuit which makes use of a frequency to phase characteristic of a resonance circuit.
Where a resistor (impedance of the real part) as a series resonance circuit element of resonance circuit 115 is absent, since Q of resonance circuit 115 is infinite, the impedance of resonance circuit 115 at series resonance frequency f.sub.s is zero (0) while the impedance of resonance circuit 115 at parallel resonance frequency f.sub.p is infinity (.infin.). Since Q can be reduced where resonance circuit 115 has, in the inside thereof, a resistor which serves as a series resonance circuit element, resonance circuit 115 is usually used with this construction. Q of resonance circuit 115 is determined by the value of the resistor which serves as the series resonance circuit element, and the demodulation sensitivity is determined by Q of resonance circuit 115.
In such conventional FM demodulation circuits as described above, since the level of input signal f.sub.in is limited to a predetermined level by an amplitude limitation circuit, it is considered that the demodulation sensitivity is fixed irrespective of the level of input signal f.sub.in.
Actually, however, there is a problem in that, when the input level becomes low (when the electric field becomes weak), the demodulation sensitivity is so lowered by an influence of the NF of the receiver and so forth that a received signal cannot be demodulated accurately.
Further, in order to raise the thus lowered demodulation sensitivity, a circuit element which forms the resonance circuit must be exchanged.
By the way, a technique of raising the demodulation sensitivity when the electric field of an FM demodulation circuit is weak is disclosed in Japanese Patent Laid-Open Application No. 204901/94 and Japanese Patent Laid-Open Application No. 156011/92. However, those documents do not disclose any technique of raising the demodulation sensitivity of a quadrature detection circuit, which is employed very frequently by receivers in recent years.